201_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

201_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 170...

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170 VLSI Test Principles and Architectures TABLE 4.2 ± OR Operation OR 01 D DX 0 0 1 D D X 1 1 1 1 1 1 D D 1 D 1 X D D 1 1 D X X X 1 X X X TABLE 4.3 ± NOT Operation NOT 0 1 1 0 D D D D X X Algorithm 1 Naive ATPG ±C²f ³ 1: while a fault-effect of f has not propagated to a PO and all possible vector combinations have not been tried do 2: pick a vector, v , that has not been tried; 3: fault simulate v on the circuit C with fault f ; 4: end while Note that in an ATPG, the worst-case computational complexity is exponential, as all possible input patterns may have to be tried before a vector is found or that the fault is determined to be undetectable. One may go about line #2 of the algorithm in an intelligent fashion, so a vector is not simply selected indiscriminately. Whether or not intelligence is incorporated, some mechanism is needed to account for those
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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