300_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

300_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic Built-In Self-Test 269 CK SRCK SE Shift Window Capture Window C1 Shift Window C2 Capture Window Shift Window • • • • • • • • • ± FIGURE 5.5 Example timing control diagram for testing data and set/reset faults. In addition, we recommend testing all data and set/reset faults using two separate BIST sessions, as shown in Figure 5.5. The timing diagram in this figure is used for testing a circuit having one system clock (CK) and one added set/reset clock. To test data faults in the functional logic, a clock pulse C1 is triggered from CK while SRCK is held inactive in one capture window. Similarly, to test set/reset faults in the set/reset circuitry, C2 is enabled while CK is held inactive in another capture window. Using this approach, we can avoid races and hazards and prevent data in scan cells from being destroyed by the set/reset signals. 5.2.1.5 Tristate Buses Bus contention occurs when two drivers force different values on the same bus
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Unformatted text preview: which can damage the chip; hence, it is important to prevent bus conflicts during normal operation as well as shift operation [Cheung 1996]. For BIST applications, since pseudo-random patterns are commonly used, it is also crucial to protect the capture operation [Al-Yamani 2002]. To avoid potential bus contention, it is best to resynthesize each bus with multiplexers. If this is impractical, make sure only one tristate driver is enabled at any given time. The one-hot decoder shown in Figure 5.6 is an example of a circuit that can ensure that only one driver is selected during each shift or capture operation. (a) (b) EN1 D1 EN2 D2 D1 D2 SE BIST_mode EN1 EN2 ± FIGURE 5.6 A one-hot decoder for testing a tristate bus with two drivers: (a) tristate bus, and (b) one-hot decoder....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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