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204_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 204_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES - X...

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Test Generation 173 Technically, whenever a decision is reversed, say d = 0 is reversed to d = 1as shown in Figure 4.8, d = 1 is no longer a decision; rather, it becomes an implied value by a subset of the previous decisions made. The exact subset of decisions that implied d = 1 can be computed by a conflict analysis [Marques-Silva 1999b]. However, the details of conflict analysis are beyond the scope of this chapter and are thus omitted. The reader can refer to [Marques-Silva 1999b] for details of this mechanism. In addition, intelligent conflict analysis can also allow for nonchrono- logical backtracking . 4.4.2 A Basic ATPG Algorithm Given a target fault g/v in a fanout-free combinational circuit C , a simple procedure to generate a vector for the fault is shown in Algorithm 2, where JustifyFanoutFree() and PropagateFanoutFree() are both recursive functions. Algorithm 2 Basic Fanout Free ATPG (C, g/v) 1: initialize circuit by setting all values to
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Unformatted text preview: X ; 2: JustifyFanoutFree ±C²g² v³ ; /* excite the fault by justifying line g to v */ 3: PropagateFanoutFree ±C²g³ ; /* propagate fault-effect from g to a PO */ The JustifyFanoutFree ±g²v³ function recursively justifies the predecessor signals of g until all signals that need to be justified are indeed justified from the primary inputs. The simple outline of the JustifyFanoutFree routine is listed in Algorithm 3. In line #10 of the algorithm, controllability measures can be used to select the best input to justify. Selecting a good gate input may help to reach a primary input sooner. Consider the circuit C shown in Figure 4.9. Suppose the objective is to justify g = 1. According to the above algorithm, the following sequence of recursive calls to JustifyFanoutFree() would have been made: a h z g f b c d ± FIGURE 4.9 Example fanout-free circuit....
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