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Unformatted text preview: 174 VLSI Test Principles and Architectures Algorithm 3 JustifyFanoutFree C g v 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: 15: g = v; if gate type of g == primary input then return; else if gate type of g == AND gate then if v == 1 then for all inputs h of g do JustifyFanoutFree C h 1 ; end for else v == 0 h = pick one input of g whose value == X; JustifyFanoutFree C h 0 ; end if else if gate type of g == OR gate then end if call call call call #1: #2: #3: #5: JustifyFanoutFree JustifyFanoutFree JustifyFanoutFree JustifyFanoutFree C C C C g 1 a 1 f 1 c 0 After these calls to JustifyFanoutFree(), abcd = 1X0X is an input vector that can justify g = 1. Consider another circuit C shown in Figure 4.10. Note that the circuit is not fanout-free, but the above algorithm will still work for the objective of trying to justify the signal g = 1. According to the algorithm, the following sequence of calls to the JustifyFanoutFree function would have been made: call call call call call #1: #2: #3: #4: #5: JustifyFanoutFree JustifyFanoutFree JustifyFanoutFree JustifyFanoutFree JustifyFanoutFree
a d c e b f z h C C C C C g 1 a 1 f 1 d 0 c 0
g FIGURE 4.10 Example circuit with a fanout structure. ...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08