208_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

208_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 177 meant for fanout-free circuits, will not always be applicable as illustrated in some of the examples above due to potential conflicts. In order to generate test vectors for general combinational circuits, there must be mechanisms that will allow the ATPG to avoid conflicts, as well as get out of a conflict when a conflict is encountered. To do so, the corresponding decision tree must be constructed during the search for a solution vector, and backtracks must be enforced for any conflict encountered. The following sections describe a few ATPG algorithms. 4.4.3 D Algorithm The D algorithm was proposed to tackle the generation of vectors in general com- binational circuits [Roth 1966] [Roth 1967]. As indicated by the name of the algo- rithm, the D algorithm tries to propagate a D or D of the target fault to a primary output. Note that because each detectable fault can be excited, a fault-effect can always be created. In the following discussion, propagation of the fault-effect will
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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