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210_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 210_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Test Generation 179 D 1 0 D propagates to PO 1 J -frontier a z y b c x FIGURE 4.14 Propagation of D - and J -frontier. to the propagation phase and attempts to propagate the fault-effect to a primary output again. The overall procedure for the D algorithm is shown in Algorithms 5 and 6. Note that the above procedure has not incorporated any intelligence in the decision-making process. In other words, sometimes it may be possible to deter- mine that some value assignments are not justifiable, given the current circuit state. For instance, consider the circuit fragment shown in Figure 4.15. Justifying gate a = 1 and gate b = 0 is not possible because a = 1 requires both of its inputs set to logic 1, while b = 0 requires both of its inputs set to logic 0. Noting such conflicting
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Unformatted text preview: scenarios early can help to avoid future backtracks. Such knowledge can be incor-porated into line #1 of the D-Alg-Recursion() shown in Algorithm 6. In particular, static and dynamic implications can be used to identify such potential conflicts, and they are used extensively to enhance the performance of the D algorithm (as Algorithm 5 D-Algorithm( C , f ) 1: initialize all gates to don’t-cares; 2: set a fault-effect ( D or D ) on line with fault f and insert it to the D-frontier; 3: J-frontier = ± ; 4: result = D-Alg-Recursion( C ); 5: if result == success then 6: print out values at the primary inputs; 7: else 8: print fault f is untestable; 9: end if...
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