212_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

212_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - Test...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Test Generation 181 line f . The algorithm then tries to propagate the fault-effect to z . First it will place a = 1inthe J -frontier, followed by h = 0inthe J -frontier. At this time, the fault- effect has reached the primary output. Now, the ATPG tries to justify all unjustified values in the J -frontier. Because a is a primary input, it is already justified. The other signals in the J -frontier are f = D and h = 0. For f = D±d = 0, thereby making c = 0. For h = 0, either e = 0or b = 0 is sufficient. Whichever one it picks, the search process will terminate, as a solution has been found. Consider the same multiplexer circuit (Figure 4.10) again. Suppose the target fault now is f stuck-at-1. Following the similar discussion as the previous target fault f/ 0, the algorithm initializes the circuit and places a D on f . Next, to propagate the fault-effect to a primary output, it likewise inserts a = 1 and h = 0 into the J -frontier. Now, the ATPG needs to justify all the gates in the
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online