218_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

218_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 187 headlines z y x g h f e d c b a ± FIGURE 4.19 Circuit with identifed headlines. a c b m = 1 k = 0 ± FIGURE 4.20 Multiple backtrace to avoid potential conflicts. to justify k = 0. The easier path may be through the fanout stem b . However, this would cause a conflict later on with the other objective m = 1. In FAN, multiple objectives are taken into account, and the backtrace routine scores the nodes visited from each objective in the current set of objectives. The nodes along the path with the best scores are chosen. In this example, a = 0 will be chosen rather than b = 0, even if a = 0 is less controllable. 4.4.6 Static Logic Implications Logic implications capture the effect of assigning logic values on other gate values
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Unformatted text preview: in a circuit. They can be extremely helpful for the ATPG to make better decisions, reduce the number of backtracks, etc. Over the past few decades, logic implications have been applied and shown their effectiveness in several areas relevant to testing. They include test-pattern-generation [Schulz 1988] [El-Maleh 1998] [Tafertshofer 2000], logic and fault simulation [Kajihara 2004], fault diagnosis [Amyeen 1999], logic verification [Paul 2000] [Marques-Silva 1999a] [Arora 2004], logic optimiza-tion [Ichihara 1997] [Kunz 1997], and untestable fault identification [Iyer 1996a] [Iyer 1996b] [Peng 2000] [Hsiao 2002] [Syal 2004]....
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