220_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

220_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 189 c a b c = 1 a = 1 b = 1 0 0 c = 0 b = 0 a = 0 0 0 ± FIGURE 4.21 Example of an implication graph. D a b c d e f g h i j k x y z w Q ± FIGURE 4.22 Sequential circuit fragment. applicable to both combinational and sequential circuits. Given the sequential cir- cuit fragment shown in Figure 4.22, consider gate f = 1: 1. Direct implications : A logic value of 1 on gate f would directly imply g = k = 1 because they are directly connected to gate f . In addition, f = 1 d = 1 and e = 1. Thus, the set ±²f³ 1 ³ 0 ´³²g³ 1 ³ 0 ´³²k³ 1 ³ 0 ´³²d³ 1 ³ 0 ´³²e³ 1 ³ 0 ´µ is the set of direct implications for f = 1. Similarly, direct implications associated with g = 1 can be computed to be ±²g³ 1 ³ 0 ´³²j³ 1 ³ 0 ´³²f³ 1 ³ 0 ´µ . These implications are stored in the form of a graph, where each node represents a gate (with a logic value). A directed edge between two nodes represents an implication, and a weight along an edge represents the relative time frame associated with the
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Unformatted text preview: implication. Figure 4.23 shows the graphical representation of a portion of direct implications for f = 1 in this example. The complete set of implications resulting from setting f = 1 can be obtained by traversing the graph rooted at node f = 1. Computing the set of all nodes reachable from this root node ²f = 1 ´ (transitive closure on f = 1) would return the set Impl¶f = 1 · . Thus, the complete set of direct implications using the implication graph shown in the figure for f = 1 is: ±²f³ 1 ³ ´³²d³ 1 ³ ´³²e³ 1 ³ ´³²g³ 1 ³ ´³²k³ 1 ³ ´³²j³ 1 ³ ´³²c³ 1 ³ − 1 ´µ...
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