225_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

225_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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194 VLSI Test Principles and Architectures E-frontier. Stated differently, the propagation of the fault effect could directly be borrowed from a previous fault. The same concept can be extended to untestable faults as well. 4.5 DESIGNING A SEQUENTIAL ATPG 4.5.1 Time Frame Expansion Test generation for sequential circuits bears much similarity with that for com- binational circuits. However, one vector may be insufficient to detect the target fault, because the excitation and propagation conditions may necessitate some of the flip-flop values to be specified at certain values. The general model for a sequential circuit is shown in Figure 4.29, where flip- flops constitute the memory/state elements of the design. All the flip-flops receive the same clock signal, so no multiple clocks are assumed in the circuit model.
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Unformatted text preview: Figure 4.30 illustrates an example of a sequential circuit which is unrolled into several time frames, also called an iterative logic array of the circuit. For each time frame, the flip-flop inputs from the previous time frame are often referred to as pseudo primary inputs with respect to that time frame, and the output signals to feed the flip-flops to the next time frame are referred to as pseudo primary outputs . Note that in any unrolled circuit, a target fault is present in every time frame. When the test generation begins, the first time frame is referred to as time frame 0. An ATPG search similar to a combinational circuit is carried out. At the end of Memory Elements Primary Outputs Primary Inputs Combinational Logic Clock ± FIGURE 4.29 Model of a sequential circuit....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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