Unformatted text preview: Figure 4.30 illustrates an example of a sequential circuit which is unrolled into several time frames, also called an iterative logic array of the circuit. For each time frame, the flip-flop inputs from the previous time frame are often referred to as pseudo primary inputs with respect to that time frame, and the output signals to feed the flip-flops to the next time frame are referred to as pseudo primary outputs . Note that in any unrolled circuit, a target fault is present in every time frame. When the test generation begins, the first time frame is referred to as time frame 0. An ATPG search similar to a combinational circuit is carried out. At the end of Memory Elements Primary Outputs Primary Inputs Combinational Logic Clock ± FIGURE 4.29 Model of a sequential circuit....
View Full Document
This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08