227_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

227_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: 196 VLSI Test Principles and Architectures At this time, a backtrack occurs in time frame 4 and the ATPG must try to find a different solution vector #4. This process is repeated. One way to reduce the complexity discussed above is to try to propagate the fault-effect in an unrolled circuit instead of propagating the fault-effect time frame by time frame. In doing so, a k-frame combinational circuit is obtained, say k = 256, and the ATPG views the entire 256-frame circuit as one large combinational circuit. However, the ATPG must keep in mind that the target fault is present in all 256 time frames. This eliminates the need to check for state boundary justifiability and allows the ATPG to propagate the fault-effect across multiple time frames at a time. When the fault-effect has been propagated to at least one primary output, the pseudo primary inputs at time frame 0 must be justified. Again, the justification can be performed in a similar process of viewing an unrolled 256-frame circuit. Ascan be performed in a similar process of viewing an unrolled 256-frame circuit....
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