228_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

228_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 197 1/0 a = 1/X 1/0 b (a) Stuck-at 0 fault at b 0/1 a = X/1 0/1 b (b) Stuck-at 1 fault at b ± FIGURE 4.31 The need for 9-valued algebra in sequential circuits. The concept of controllability and observability metrics can be extended to sequential circuits such that the backtrace routine would prefer to backtrace toward primary inputs and those easy-to-justify flip-flops. Using sequential testability met- rics allows the ATPG to narrow the search space by favoring the easy-to-reach states and avoiding getting into difficult-to-justify states. The computational complexity of a sequential ATPG is intuitively higher than that of the combinational ATPG. Therefore, aggressive learning can help to reduce the computational cost. For instance, if a known subset of unreachable states is available, this information can be used to allow the ATPG to backtrack much sooner when an intermediate state is unreachable. This can avoid successive justification
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Unformatted text preview: of an unreachable state. Likewise, if a justification sequence has been successfully computed for state S before, and a different target fault requires the same state S , the previous justification sequence can be used to guide the search. Note that, because the target faults are different, the justification sequence may not simply be copied from the solution for one fault to another. 4.5.3 Gated Clocks and Multiple Clocks All the algorithms for sequential ATPG thus far assumed the sequential circuit has a single global clock. This assumption is simple as all memory elements (flip-flops) switch synchronously at every clock; however, in modern digital systems, this assumption is often not true. For instance, gated clocks (illustrated in Figure 4.32a) and multiple clocks (Figure 4.32b) are becoming mainstream. Gated clocks are...
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