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198 VLSI Test Principles and Architectures (a) Gated Clock (b) Multiple Clocks D b a Clock Q D D Clock2 Clock1 b a Q Q FIGURE 4.32 Non-traditional clocking schemes. mostly used for power savings, such that not all memory elements will switch at every clock. On the other hand, multiple clocks benefit performance, power, and design as blocks can be partitioned to different clock domains. If circuit modification is not possible, ATPG should be designed to perform some circuit modeling as a preprocessing step to ease the ATPG process. Actually, this is the approach taken by most current EDA vendors today. In other words, instead of designing new ATPG algorithms that can handle designs with gated clocks and multiple clocks, it may be easier to slightly modify the circuit such that the original circuit is transformed to one that uses only a single, global clock such that the transformed circuit is functionally equivalent to the original design. For instance, consider the gated clock case. The memory element that depends on a gated clock
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