198VLSI Test Principles and Architectures(a) Gated Clock(b) Multiple ClocksDbaClockQDDClock2Clock1baQQFIGURE 4.32Non-traditional clocking schemes.mostly used for power savings, such that not all memory elements will switch atevery clock. On the other hand, multiple clocks benefit performance, power, anddesign as blocks can be partitioned to different clock domains.If circuit modification is not possible, ATPG should be designed to perform somecircuit modeling as a preprocessing step to ease the ATPG process. Actually, thisis the approach taken by most current EDA vendors today. In other words, insteadof designing new ATPG algorithms that can handle designs with gated clocks andmultiple clocks, it may be easier to slightly modify the circuit such that the originalcircuit is transformed to one that uses only a single, global clock such that thetransformed circuit is functionally equivalent to the original design. For instance,consider the gated clock case. The memory element that depends on a gated clock
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