230_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

230_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 199 D b Clock a D 0 1 Clock a b D 0 1 Clock a b D a b Q Q Q Q ± FIGURE 4.33 Transformation of gated clock. Clock2 Clock1 b a f (Clock1, Clock2) new a new b D Q D Q DQ Q D ± FIGURE 4.34 Transformation of multiple clocks. Note, however, fault models other than the stuck-at model may not necessarily benefit from this transformation. Finally, alternatives to the above MUX-based modifications are possible for han- dling designs with multiple clocks. They include the one-hot or the staggered clock- ing schemes. The details of the clocking are described in Section 5.7. One-hot clocking gives better fault coverage, but it suffers from potential large test sets.
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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