200VLSI Test Principles and Architectureswith staggered or simultaneous clocking schemes, then a one-hot clocking schemeis used to detect any remaining faults [Wang 2003].4.6UNTESTABLE FAULT IDENTIFICATIONUntestable faults are faults for which there exists no test pattern that can bothexcite the fault and propagate its fault-effect to a primary output. Thus, a fault maybe untestable for any of the following three reasons:The conditions necessary to excite the fault are not possible.The conditions necessary to propagate the fault-effect to a primary output arenot possible.The conditions for fault excitation and fault propagation cannot be simulta-neously satisfied.In combinational circuits, untestable faults are due to redundancies in the circuit,while in sequential circuits untestable faults may also result from the presence ofunreachable states or impossible state transitions.From an ATPG’s point of view, the presence of untestable faults in a design candegrade the performance of the ATPG tool. When considering untestable faults, an
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Computational complexity theory, The Circuit, Iyer, ATPG