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238_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 238_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Test Generation 207 Algorithm 12 Multi-Line-Conﬂicts() 1: construct implication graph; 2: /* identification of impossible combinations */ 3: for each gate assignment g = val do 4: identify the TNC for g = val ; 5: Impossible Combination (IC) set = TNC, g = val ; 6: i = 0, S untest = ∅ ; 7: for each assignment a = w in IC do 8: S i = fault untestable with a = w ; 9: if i == 0 then 10: S untest = S untest S i ; 11: else 12: S untest = S untest S i ; 13: end if 14: if S untest = ∅ then 15: break; 16: else 17: i ++ ; 18: end if 19: end for 20: end for Proof Because b = w is not a terminating necessary condition for g = u , there must exist some necessary conditions to achieve b = w . Now, because a = v is a terminating condition for g = u and because a and b are related, then a = v must be a part of the conditions necessary to set b = w . This means that in order to set b = w , gate a must be set to v , or in other words, b w 0 a v 0 . By contrapositive law, a v 0 b w 0 . Thus, impl a v 0 impl b w 0 . Thus, according to Lemma 2, the implications of the complement of all elements in
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