208VLSI Test Principles and Architectures4.7.1OverviewAs we have already seen earlier in this chapter, the random test generator is asimple type of simulation-based ATPG. The vectors are randomly generated andsimulated on the circuit under test, and any vector that is capable of detecting newfaults is added to the test set. While this concept is relatively simple, its applicabilityis limited as random ATPG cannot generate vectors that target hard faults.Simulation-based test generators were first proposed in 1962 by Seshu andFreeman [Seshu 1962]. Subsequently, several other simulation-based test genera-tors have been developed, including [Breuer 1971], [Schnurmann 1975], [Lisanke1987], [Wunderlich 1990], [Snethen 1977], and [Agrawal 1989]. Each of these testgenerators will be described in the following discussion.Random vectors are simulated and selected using a fault simulator in [Breuer1971]. Weighted random test generators were introduced in [Schnurmann 1975],[Lisanke 1987], and [Wunderlich 1990], in which each bit is generated with a biased
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