239_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

239_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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208 VLSI Test Principles and Architectures 4.7.1 Overview As we have already seen earlier in this chapter, the random test generator is a simple type of simulation-based ATPG. The vectors are randomly generated and simulated on the circuit under test, and any vector that is capable of detecting new faults is added to the test set. While this concept is relatively simple, its applicability is limited as random ATPG cannot generate vectors that target hard faults. Simulation-based test generators were first proposed in 1962 by Seshu and Freeman [Seshu 1962]. Subsequently, several other simulation-based test genera- tors have been developed, including [Breuer 1971], [Schnurmann 1975], [Lisanke 1987], [Wunderlich 1990], [Snethen 1977], and [Agrawal 1989]. Each of these test generators will be described in the following discussion. Random vectors are simulated and selected using a fault simulator in [Breuer 1971]. Weighted random test generators were introduced in [Schnurmann 1975], [Lisanke 1987], and [Wunderlich 1990], in which each bit is generated with a biased
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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