254_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

254_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 223 00 11 12 23 S 1 states: 0 1 2 S 2 states: 0 1 2 3 Partitioned States S 1 and S 2 (2 sets of four flip-flops) Global State S (8 flip-flops) Current Global State Table Current Partitioned State Table ± FIGURE 4.44 State partition examples. Different states on the datapath generally map to different operand values for the functional units in the design, while different states in the controller dictate different modes of operation for the circuit. This implies that the underlying ATPG should not treat the entire state as one entity. In other words, treating the entire state as one entity may mislead the test generator, particularly by the “noise” from those unimportant states . Thus, partitioning of state will help to weed out the noise. State partitioning can remove the noise and provide better guidance in the search space, as shown in Figure 4.44. In Figure 4.44, consider a circuit with eight flip-flops. Let the global state, S , be partitioned into two partial states, S
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