258_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

258_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 227 of vectors for some undetected faults, some untestable faults are also identified. Simulation-based test generation may resume after a test sequence is obtained from the deterministic procedure. There are of course other methods of combining simulation-based and determin- istic algorithms for test generation. The GA–HITEC hybrid test generator [Rudnick 1995] uses deterministic algorithms for fault excitation and propagation and a GA for state justification. Deterministic procedures for state justification are used if the GA is unsuccessful. Instead of targeting one group of faults at a time, GA-HITEC targets one fault at a time, as is generally done in deterministic ATPGs. This particular method of combination in GA-HITEC is based on the observa- tion that deterministic algorithms for combinational circuit test generation have proven to be more effective than genetic algorithms [Rudnick 1994]. Furthermore, in sequential circuits, state justification using deterministic approaches is known
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Unformatted text preview: to be very difficult and is vulnerable to many backtracks, leading to excessive exe-cution times. Therefore, it makes sense to include the deterministic algorithm for fault excitation and propagation, while the GA is used for state justification. Note that this approach cannot identify some untestable faults. In GA-HITEC, a fault is taken as a target. Then, the fault is excited by the deterministic engine, followed by propagation to a primary output, perhaps through several time frames, also by the deterministic engine. Through this process, several primary inputs and flip-flop variables at time frame 0 would have been chosen as decision points, as illustrated in Figure 4.46. The decisions made on the flip-flops x 1 x x x 1 x x 10101 00111 11010 Step 1: Deterministic ATPG in time-frame zero to derive a combinational vector Step 2: GA to derive the justification sequence Target State 1 1/0 s-a-0 1 s-a-0 s-a-0 s-a-0 ± FIGURE 4.46 Test generation using GA for state justiFcation....
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