260_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

260_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 229 A fast run of a GA-based test generator is followed by a run of a deterministic test generator that targets faults that were left undetected by the previous GA-based test generator. Any successful sequences derived by the deterministic test generator are used as seeds for the successive GA-based ATPG run. The test sequences derived by the deterministic engine typically will traverse previously unvisited states. Thus, the deterministic test generator may be viewed as an external engine whose purpose is mainly to guide the GA to new state spaces of the circuit that have not been visited. By visiting new state spaces, the test generator can maximize the search space. Furthermore, the use of a deterministic test generator also helps to identify any untestable faults, thus saving the computational effort in the GA runs on those faults that could never be detected. The test generation process in ALT-TEST is divided into three stages; each of the three stages is composed of alternating phases of GA-based and HITEC test
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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