263_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

263_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 232...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
232 VLSI Test Principles and Architectures testing can catch some delay defects, the stuck-at fault model is insufficient to model delay defects satisfactorily. This has prompted engineers and researchers to propose a variety of methods and fault models for detecting speed failures. Among the fault models are the transition fault [Levendel 1986] [Waicukauski 1987] [Cheng 1993], the path-delay fault [Smith 1985], and the segment delay fault [Heragu 1996]. This section is devoted to path-delay fault test generation. The path-delay fault model considers the cumulative effect of the delays along a specific combinational path in the circuit. If the cumulative delay in a faulty circuit exceeds the clock period for the path, then the test pattern that can exercise this path will fail the chip. The segment delay fault model targets path segments instead of complete paths. Because a transition has to be launched in order to propagate across a given path, two vectors are needed. The first vector initializes the circuit nodes, and the second
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online