265_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

265_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
234 VLSI Test Principles and Architectures d c a e b Path: abce ± FIGURE 4.48 A statically unsensitizable but not false path. X 0 S 1 X 0 a g f e d c b ± FIGURE 4.49 A robustly testable path. propagation of the falling transition from b to d is independent of the value of a in the first vector (and similarly for the transition from f to g ). On the other hand, a steady 1 (S1) is needed for both the first and second vectors on signal c . Relaxing the value in the first vector could block the transition from d to f . The target path in the above example is said to be robustly testable . More specifically, the path is testable irrespective of other delay faults in the circuit [Smith 1985] [Lin 1987]. In the same running example shown in Figure 4.49, if the
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: “don’t care” value in the first vector for signal a is a logic 1, the transition on b would still be propagated to d , as the transition on d depends on the later of the two transitions. In short, a delay on a will not prevent the target path from being detected. Given the above discussion, the value criteria for each off-input of P for a robustly testable path are as follows: ± When the corresponding on-input of P has a controlling to noncontrolling transition, the value in the first vector for the off-input can be “don’t care,” with the value for the off-input as a noncontrolling value in the second vector....
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online