267_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

267_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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236 VLSI Test Principles and Architectures Given the above discussion, the value criteria for each off-input of P for a nonro- bustly testable path are as follows: ± Irrespective of the transition on the on-input, the value in the first vector for the off-input can be “don’t care,” with the value for the off-input as a noncontrolling value in the second vector. There are other classes of path-delay faults, such as validatable nonrobustly testable path-delay faults, functional sensitizable path-delay faults, multi-path-delay faults, etc . They are not included in this discussion. 4.10.1.2 ATPG for Path-Delay Faults Unlike stuck-at test generation, where only one vector is necessary and the value on any signal can be 0, 1, D , D ,or X , in path-delay fault test generation, two vectors are required, and the vector pair only has to ensure that a transition is launched at the start of the path and that the off-inputs satisfy the conditions specified by the robust or non-robust tests. For a given target path
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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