269_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

269_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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238 VLSI Test Principles and Architectures 4.10.2 ATPG for Transition Faults If robust tests were possible for all the paths in a circuit, we would not need any additional test vectors for capturing the delay defects. However, because very few paths are robustly testable, there will be some delays that cannot be captured by either robust or nonrobust path-delay fault tests. Consider the situation where some small delay defects are distributed inside a circuit. If the circuit nodes lie on a robustly untestable path or a less critical path, then the path-delay fault test vectors may miss those faults. The segment delay fault model might also miss the faults because there might not be a path along which the effect may be propagated. A transition fault at node g assumes a delay defect is present at node g such that the propagation of the transition at g will not reach the flip-flop or primary output within the clock period. While the path-delay fault model considers the cumulative effect of the delays along a specific path, the transition fault model
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