271_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

271_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
240 VLSI Test Principles and Architectures 4.10.3 Transition ATPG Using Stuck-At ATPG A transition fault can be modeled as two stuck-at faults. Thus, one can view testing transition faults as testing two stuck-at faults. For example, a transition fault a slow- to-rise can be modeled as exciting the fault a/ 1 in the first time frame and detecting the fault a/ 0 in the second time frame. In other words, exciting a/ 1 requires setting a = 0, and testing for a/ 0 requires setting a = 1 and propagating its effect to an observable point. With enhanced-scan, because the two vectors are not correlated, these two vectors can be generated independently. For launch-on-capture or launch-on-shift, the two time frames must be handled together. In the launch-on-capture-based test scheme, one may view the excitation of the fault in the first time frame as a constraint for the ATPG for detecting the fault in the second time frame. In other words, for testing the transition fault a slow-to-rise, the stuck-at fault
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online