280_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

280_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Test Generation 249 faults is also covered, with emphasis on those fault models that address delay defects, such as the path-delay fault and the transition fault. Finally, additional topics are briefly addressed that relate to the topic of test generation. 4.13 EXERCISES 4.1 (Random Test Generation) Given a circuit with three primary outputs, x±y , and z , the fanin cone of x is ²a±b±c³ , the fanin cone of y is ²c±d±e±f³ , and the fanin cone of z is ²e±f±g³ . Devise a pseudo-exhaustive test set for this circuit. Is this test set the minimal pseudo-exhaustive test set? 4.2 (Random Test Generation) Using the circuit shown in Figure 4.10, compute the detection probabilities for each of the following faults:
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: a. e/ b. e/ 1 c. c/ 4.3 (Boolean Difference) Using the circuit shown in Figure 4.10, compute the set of all vectors that can detect each of the following faults using Boolean difference: a. e/ b. e/ 1 c. c/ 4.4 (Boolean Difference) Using the circuit shown in Figure 4.16, compute the set of all vectors that can detect each of the following faults using Boolean difference: a. a/ 1 b. d/ 1 c. g/ 1 4.5 (Boolean Difference) Using the circuit shown in Figure 4.35, compute the set of all vectors that can detect each of the following faults using Boolean difference: a. a/ 1 b. b 1 / 1 c. e/ d. e 2 / 1...
View Full Document

Ask a homework question - tutors are online