281_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

281_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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250 VLSI Test Principles and Architectures 4.6 (Boolean Difference) Assume a single-output combinational circuit, where the output is denoted as f . If two faults, ± and ² , are indistinguishable, it means that there does not exist a vector that can detect only one and not the other. Show that f ± f ² = 0 if they are indistinguishable. 4.7 ( D Algorithm) Construct the table for the XNOR operation for the 5-valued logic similar to Tables 4.1, 4.2, and 4.3. 4.8 ( D Algorithm) Using the circuit shown in Figure 4.35, use the D algorithm to compute a vector for the fault b/ 1. Repeat for the fault e/ 0. 4.9 ( D Algorithm) Consider a three-input AND gate g . Suppose g D -frontier. What are all the possible value combinations the three inputs of g can take such that g is a valid D -frontier? 4.10 (PODEM) Repeat Problem 4.8 using PODEM instead of the D algorithm. 4.11 (PODEM) Using the circuit shown in Figure 4.22, compute the vector that
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Unformatted text preview: can detect the fault f/ 0. Note that even though the circuit is sequential it can be viewed as a combinational circuit because the D flip-flop does not have an explicit feedback. 4.12 (Static Implications) Using the circuit shown in Figure 4.22 and given the fact that the implications of f = 1 are shown in Figure 4.25, how could you use this information as multiple objectives to speed up the test generation for the fault f/ 0? 4.13 (Static Implications) Construct the static implication graph for the circuit shown in Figure 4.57 with only indirect implications. Based on the implica-tion graph: a. What are all the implications for g = 0? b. What are all the implications for f = 0? c b a e g h d f ± FIGURE 4.57 Example circuit....
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