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282_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 282_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES - D...

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Test Generation 251 4.14 (Static Implications) Construct the static implication graph for the circuit shown in Figure 4.58 by considering: a. Only direct implications b. Direct and indirect implications, including those obtained by the contra- positive law z g f e d c b a FIGURE 4.58 Example circuit. 4.15 (Dynamic Implications) Consider the circuit shown in Figure 4.58. Suppose justifying e = 1 via a = 0 is not possible due to some prespecified constraints. Perform all dynamic implications for all signals based on the knowledge of this constraint. 4.16 (Dynamic Implications) Prove that two faults, f and g , in a combinational circuit with the same E-frontier that has at least one
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Unformatted text preview: D or D , can be propagated to a primary output the same way. 4.17 (Untestable Fault Identification) Consider the circuit shown in Figure 4.58. a. Compute the static logic implications of b = 0. b. Compute the static logic implications of b = 1. c. Compute the set of faults that are untestable when b = 0. d. Compute the set of faults that are untestable when b = 1. e. Compute the set of untestable faults based on the stem analysis of b . 4.18 (PODEM) Consider the circuit shown in Figure 4.58, and use PODEM to generate a vector for each of the following faults: a. c/ b. c/ 1 c. d/ d. d/ 1...
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