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Unformatted text preview: D or D , can be propagated to a primary output the same way. 4.17 (Untestable Fault Identification) Consider the circuit shown in Figure 4.58. a. Compute the static logic implications of b = 0. b. Compute the static logic implications of b = 1. c. Compute the set of faults that are untestable when b = 0. d. Compute the set of faults that are untestable when b = 1. e. Compute the set of untestable faults based on the stem analysis of b . 4.18 (PODEM) Consider the circuit shown in Figure 4.58, and use PODEM to generate a vector for each of the following faults: a. c/ b. c/ 1 c. d/ d. d/ 1...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
 Spring '08
 elbarki

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