283_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 283_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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252 VLSI Test Principles and Architectures 4.19 (Untestable Fault Identification) Consider the circuit shown in Figure 4.59. a z k j i h g f e d c b ± FIGURE 4.59 Example circuit. a. Compute the static logic implications of b = 0. b. Compute the static logic implications of b = 1. c. Compute the set of faults that are untestable when b = 0. d. Compute the set of faults that are untestable when b = 1. e. Compute the set of untestable faults based on the stem analysis of b . 4.20 (PODEM) Consider the circuit shown in Figure 4.59, and use PODEM to generate a vector for each of the following faults: a. k/ 1 b. k/ 0 c. g/ 1 d. g/ 0 4.21 (Untestable Fault Identification) Prove that any fault that is combination-
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Unformatted text preview: ally untestable is also sequentially untestable. 4.22 (FAN) Consider the circuit shown in Figure 4.19. Suppose the constraint that y = 1 → x = 0 is given. How could one use this knowledge to reduce the search space when trying to generate vectors in the circuit? For example, suppose the target fault is y/ 0. 4.23 (Sequential ATPG) Consider the circuit shown in Figure 4.60. The target fault is a/ 0. a. Generate a test sequence for the target fault using only 5-valued logic. b. Generate a test sequence for the target fault using 9-valued logic....
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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