Unformatted text preview: Consider an iterative logic array (ILA) expansion of a sequential circuit, where the initial pseudo primary inputs are fully control-lable. Show that the states reachable in successive time frames of the ILA shrink monotonically. 4.27 (Simulation-Based ATPG) Design a simple genetic-algorithm based ATPG for combinational circuits. Design the fitness to be the number of faults detected. Adjust the GA parameters to observe the effectiveness of the test generator....
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- Spring '08
- Natural number, Finite set, sequential circuit