284_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

284_pdfsam_VLSI - Consider an iterative logic array(ILA expansion of a sequential circuit where the initial pseudo primary inputs are fully

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Test Generation 253 D z a Q ± FIGURE 4.60 Example sequential circuit. 4.24 (Sequential ATPG) Given a sequential circuit, is it possible that two stuck-at faults, a/ 0 and a/ 1, are both detected by the same vector v i in a test sequence v 0 ±v 1 ±²²²±v k ? 4.25 (Sequential ATPG) Consider the sequential circuit shown in Figure 4.61. If the initial state is de = 00, what is the set of reachable states? Draw the corresponding state diagram for the finite state machine. D D j i h g f e d c b a Q Q ± FIGURE 4.61 Example sequential circuit. 4.26 (Sequential ATPG)
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Unformatted text preview: Consider an iterative logic array (ILA) expansion of a sequential circuit, where the initial pseudo primary inputs are fully control-lable. Show that the states reachable in successive time frames of the ILA shrink monotonically. 4.27 (Simulation-Based ATPG) Design a simple genetic-algorithm based ATPG for combinational circuits. Design the fitness to be the number of faults detected. Adjust the GA parameters to observe the effectiveness of the test generator....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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