285_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

285_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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254 VLSI Test Principles and Architectures 4.28 (Simulation-Based ATPG) Design a simple genetic-algorithm-based ATPG for sequential circuits, where an individual is a concatenation of several vectors. Design the fitness to be the number of faults detected. Adjust the GA parameters to observe the effectiveness of the test generator. 4.29 (Advanced Simulation-Based ATPG) Illustrate an example where a sequence that is able to propagate a fault-effect from a flip-flop FF i to a pri- mary output for fault f 1 cannot propagate a fault effect at the same flip-flop FF i for a different fault f j . 4.30 (Hybrid ATPG) Consider a fault f that is aborted by both deterministic and simulation-based test generators. a. What characteristics can be said for f considering that it is aborted by a deterministic ATPG?
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Unformatted text preview: b. What characteristics can be said for f considering that it is aborted by a simulation-based ATPG? c. Suppose a hybrid ATPG detects f ; what synergy is explored to detect f ? 4.31 (Path-Delay ATPG) Consider the circuit fragment shown in Figure 4.62. a b c d e f g h i j ± FIGURE 4.62 Example circuit. a. Generate all paths in this circuit. How many paths are there in this circuit? b. Which paths are functionally unsensitizable? c. For those sensitizable paths, which ones are robustly testable, and which ones are nonrobustly testable? 4.32 (Path-Delay ATPG) Given a combinational circuit with the knowledge of the implication a = 1 → b = 1. How can this knowledge be used to deduce certain paths are unsensitizable?...
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