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286_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 286_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Test Generation 255 4.33 (Path-Delay ATPG) Construct the table for the XNOR operation for the 5-valued system similar to Tables 4.12, 4.13, and 4.14. 4.34 (Path-Delay ATPG) Consider a full-scan circuit. Discuss how incidental detection of a sequentially untestable path-delay fault in the full-scan mode can lead to yield loss. 4.35 (Transition Test Chains) Consider the dictionary of excited and detected stuck-at faults of a test set shown in Table 4.18. Construct the smallest set of vectors that can detect as many transition faults as possible using only these seven stuck-at vectors. TABLE 4.18 Fault Dictionary Without Fault Dropping Vectors Excited Faults Detected Faults V 1 a/ 0 b/ 0 c/ 0 d/ 0 e/ 1 f/ 1 V 2 c/ 0 f/ 0 g/ 0 h/ 0 e/ 1 f/ 1 V 3 d/ 0 e/ 0 h/ 0 i/ 0 a/ 1 b/ 1 c/ 1 f/ 1 g/ 1 V 4 a/ 0 b/ 0 g/ 0 i/ 0 d/ 1 e/ 1 f/ 1 V 5 c/ 0 d/ 0 g/ 0 a/ 1 d/ 1 h/ 1 i/ 1 V 6 d/ 0 e/ 0 i/ 0 a/ 1 b/ 1 c/ 1 f/ 1 g/ 1 V 7 b/ 0 g/ 0 e/ 1 i/ 1 4.36 (Bridging Faults) Consider a bridging fault between the outputs of an AND gate x = ab and an OR gate y = c + d . What values to abcd would induce the largest current in the bridge? 4.37 (A Design Practice) Use the pseudo-random pattern generator
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Unformatted text preview: Use the pseudo-random pattern generator and the ATPG program provided online to generate test sets for a number of combinational benchmark circuits. Compare and contrast the execution time and fault coverage obtained by the random TPG and the ATPG. What benefits does each have? 4.38 (A Design Practice) Repeat Problem 4.37 for sequential bench-mark circuits. 4.39 (A Design Practice) Use the pseudo-random pattern generator provided online to generate test sets for a number of combina-tional benchmark circuits. Then, use the ATPG program also provided online to generate test vectors only for those undetected faults by the random vectors. Compare and contrast the execution time and fault coverage obtained by such a combined random and deterministic approach. 4.40 (A Design Practice) Repeat Problem 4.39 for sequential bench-mark circuits....
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• Spring '08
• elbarki
• Automatic test pattern generation, ATPG, design practice, benchmark circuits, combinational benchmark circuits

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