[Iyer 1996a] M. A. Iyer and M. Abramovici, FIRE: a fault independent combinational redun-
IEEE Trans. VLSI Syst.
, 4(2), 295–301, 1996.
[Iyer 1996b] M. A. Iyer, D. E. Long, and M. Abramovici, Identifying sequential redundancies
without search, in
Proc. of Design Automation Conf.
, June 1996, pp. 457–462.
[Kajihara 2004] S. Kajihara, K. K. Saluja, and S. M. Reddy, Enhanced 3-valued logic/fault
simulation for full scan circuits using implicit logic values, in
Proc. IEEE European Test
., May 2004, pp. 108–113.
[Kunz 1993] W. Kunz and D. K. Pradhan, Accelerated dynamic learning for test pattern
generation in combinational circuits,
IEEE Trans. Comput.-Aided Des.
, 12(5), 684–694,
[Kunz 1994] W. Kunz and D. K. Pradhan, Recursive learning: a new implication technique for
efficient solutions to CAD problems—test, verification, and optimization,