Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 258 VLSI Test Principles and Architectures [Zhao 2001] J. Zhao, J. A. Newquist, and J. H. Patel, A graph traversal based framework for sequential logic implication with an application to C-cycle redundancy identification, in Proc. IEEE Int. Conf. on VLSI Design , January 2001, pp. 163–169. R4.5—Designing a Sequential ATPG [Kirkland 1987] T. Kirkland and M. R. Mercer, A topological search algorithm for ATPG, in Proc. IEEE Design Automation Conf. , June 1987, pp. 502–508. [Muth 1976] P. Muth, A nine-valued circuit model for test generation, IEEE Trans. Comput. , C-25(6), 630–636, 1976. [Niermann 1991] T. M. Niermann and J. H. Patel, HITEC: a test generation package for sequential circuits, in Proc. European Design Automation Conf. , February 1991, pp. 214–218. [Wang 2003] L.-T. Wang, K.S. Abdel-Hafez, X. Wen, B. Sheu, and S.-M. Wang, Smart ATPG (Automatic Test Pattern Generation) for Scan-Based Integrated Circuits, U.S. Patent Application No. 20050262.409, May 23, 2003 (allowed May 2, 2006).Application No....
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online