292_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

292_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 261 [Saab 1994] D. G. Saab, Y. G. Saab, and J. A. Abraham, Iterative [simulation-based genetics + deterministic techniques] = complete ATPG, in Proc. IEEE Int. Conf. on Comput.-Aided Des. , November 1994, pp. 40–43. R4.10—ATPG for Non-Stuck-At Faults [Bhawmik 1997] S. Bhawmik, Method and Apparatus for Built-In Self-Test with Multiple Clock Circuits, U.S. Patent No. 5,680,543, 1997. [Cheng 1993] K. T. Cheng, S. Devadas, and K. Keutzer, Delay-fault test generation and synthe- sis for testability under a standard scan design methodology, IEEE Trans. Comput.-Aided Des. , 12(8), 1217–1231, 1993. [Dervisoglu 1991] B. Dervisoglu and G. Stong, Design for testability: using scanpath tech- niques for path-delay test and measurement, in Proc. IEEE Int. Test Conf. , October 1991, pp. 365–374. [Devadas 1993] S. Devadas, K. Keutzer, and S. Malik, Computation of floating mode delay in combinational circuits: theory and algorithms, IEEE Trans. Comput.-Aided Des. , 12(12), 1913–1923, 1993. [Fuchs 1994] K. Fuchs, M. Pabst, and T. Rossel, RESIST: a recursive test pattern generation
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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