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262 VLSI Test Principles and Architectures During Self-Test or Scan-Test, U.S. Patent Application No. 20,020,120,896, August 29, 2002. [Williams 1973] M. J. Y. Williams and J. B. Angel, Enhancing testability of large-scale integrated circuits via test points and additional logic, IEEE Trans. Comput. , C-22(1), 46–60, 1973. R4.11—Other Topics in Test Generation [Chang 1998] J. T.-Y. Chang, C.-W. Tseng, C.-M. J. Li, M. Purtell, and E. J. McCluskey, Analysis of pattern-dependent and timing-dependent failures in an experimental test chip, in Proc. IEEE Int. Test Conf. , October 1998, pp. 184–193. [Dworak 2000] J. Dworak, M. R. Grimaila, S. Lee, L.-C. Wang, and M. R. Mercer, Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D, in Proc. IEEE Int. Test Conf. , October 2000, pp. 930–939. [Franco 1995] S. C. Ma, P. Franco, and E. J. McCluskey, An experimental chip to evaluate test
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Unformatted text preview: technique experiment results, in Proc. IEEE Int. Test Conf. , October 1995, pp. 663–672. [Kim 2001] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, Combinational test generation for various classes of acyclic sequential circuits, Proc. IEEE Int. Test Conf. , October 2001, pp. 1078–1087. [Pomeranz 1991] I. Pomeranz, L. N. Reddy, and S. M. Reddy, COMPACTEST: a method to generate compact test sets for combinatorial circuits, Proc. IEEE Int. Test Conf. , October 1991, pp. 194–203. [Reddy 1997] S. M. Reddy, I. Pomeranz, and S. Kajihara, Compact test sets for high defect coverage, IEEE Trans. Comput.-Aided Des. , 16(8), 923–930, 1997. [Rudnick 1999] E. M. Rudnick and J. H. Patel, Efficient techniques for dynamic test sequence compaction, IEEE Trans. Comput.-Aided Des. , 48(3), 323–330, 1999....
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