270-W08-EXAM02solns-V2

# 270-W08-EXAM02solns-V2 - The University of Michigan EECS...

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The University of Michigan EECS 270: Introduction to Logic Design Winter 2008 Exam 2 Solutions Professor John P. Hayes Professor Kang. G. Shin Wednesday March 19, 2008 8:00 to 9:30 pm Name: ________________________________ UMID: ________________________________ Honor Pledge: Honor Pled “I have neither given nor received aid on this exam, nor have I concealed any violations of the Honor Code.” Signature: ____________________________ ge: 1: _______ /10 2: _______ /20 3: _______ /10 4: _______ /10 5: _______ /10 6: _______ /20 7: _______ /20 Total : ______ /100 Instructions The exam is closed book . No books, notes or the like may be used. No computers, calculators, PDAs, cell phones or other electronic devices may be used Print your name, give your UMID, and sign the Honor Pledge above when you are done. Show all your work . You get partial credit for partial answers. The exam consists of eight problems with the point distribution indicated on the right. Please keep this in mind as you work 1

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Problem 1 : [ Multifunction Registers : 10 points] Using D flip-flops and multiplexers, design a 4-bit universal shift register that has the following 4 modes of operation: - Hold (preserve current data): Mode=00 - Parallel Load (Inputs L3,L2,L1,L0): Mode=01 - Shift Left: Mode=10 - Shift Right: Mode=11 Complete the following circuit (you must also connect external inputs L3, L2, L1, L0 as well as serial left input L, and serial right input R). 3 2 1 0 S1 S0 4x1 MUX 3 2 1 0 S1 S0 4x1 MUX 3 2 1 0 S1 S0 4x1 MUX 3 2 1 0 S1 S0 4x1 MUX Mode D Q > Q3 D Q > Q2 D Q > Q1 D Q > Q0 Clock Right Left RL 3 L 2 L 1 L 0 L 2
Problem 2 : [ Toggle Circuits : 20 points] a. [6 points] Design a toggle flip-flop T with a D flip-flop where T’s output toggles (from 1 to 0, or from 0 to 1) whenever a button X is pressed then released. You should not use any extra logic gates. Note that no extra gates are needed because X is connected to the D flip-flop’s clock input. 0 5 10 15 20 25 30 35 b. [8 points] Complete the following waveforms for the above circuit. Assume all devices initially store a 0 and have a delay of 1 time unit. X Q0 Q1 Q2 1 0 1 0 1 0 1 0 3

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4-bit Parallel Counter L3 L2 L1 L0 Q3 Q2 Q1 Q0 CNT LD RST Clock 0 0 1 1 1 c. [6 points] Design a counter that counts 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 5, 6, 7, … using a modulo 16 counter shown below and as few additional logic gates as possible. Note that you also need to set data and control inputs appropriately.
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## This test prep was uploaded on 04/04/2008 for the course EECS 270 taught by Professor Hayes during the Winter '08 term at University of Michigan.

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270-W08-EXAM02solns-V2 - The University of Michigan EECS...

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