registers and counters.ppt - ECE-135 REGISTERS AND COUNTERS MOHINDER BASSI Lecture 13 Sequential Logic Counters and Registers Counters Introduction

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ECE-135 REGISTERS AND COUNTERS MOHINDER BASSI
CS1104-13 Lecture 13: Sequential Logic: Counters and Registers 2 Lecture 13: Sequential Logic Counters and Registers Counters Introduction: Counters Asynchronous (Ripple) Counters Asynchronous Counters with MOD number < 2 n Asynchronous Down Counters Cascading Asynchronous Counters
CS1104-13 Lecture 13: Sequential Logic: Counters and Registers 3 Lecture 13: Sequential Logic Counters and Registers Synchronous (Parallel) Counters Up/Down Synchronous Counters Designing Synchronous Counters Decoding A Counter Counters with Parallel Load
CS1104-13 Lecture 13: Sequential Logic: Counters and Registers 4 Lecture 13: Sequential Logic Counters and Registers Registers Introduction: Registers Simple Registers Registers with Parallel Load Using Registers to implement Sequential Circuits Shift Registers Serial In/Serial Out Shift Registers Serial In/Parallel Out Shift Registers Parallel In/Serial Out Shift Registers Parallel In/Parallel Out Shift Registers
CS1104-13 Lecture 13: Sequential Logic: Counters and Registers 5 Lecture 13: Sequential Logic Counters and Registers Bidirectional Shift Registers An Application – Serial Addition Shift Register Counters Ring Counters Johnson Counters Random-Access Memory (RAM)
CS1104-13 Introduction: Counters 6 Introduction: Counters Counters are circuits that cycle through a specified number of states. Two types of counters: synchronous (parallel) counters asynchronous (ripple) counters Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops. Synchronous counters apply the same clock to all flip-flops.
CS1104-13 Asynchronous (Ripple) Counters 7 Asynchronous (Ripple) Counters Asynchronous counters : the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters , as the input clock pulse “ripples” through the counter – cumulative delay is a drawback. n flip-flops a MOD (modulus) 2 n counter. (Note: A MOD- x counter cycles through x states.) Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider .
CS1104-13 Asynchronous (Ripple) Counters 8 Asynchronous (Ripple) Counters Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock input of the next more-significant flip-flop. K J K J HIGH Q 0 Q 1 Q 0 FF1 FF0 CLK C C Timing diagram 00 01 10 11 00 ... 4 3 2 1 CLK Q 0 Q 0 Q 1 1 1 1 1 0 0 0 0 0 0
CS1104-13 Asynchronous (Ripple) Counters 9 Asynchronous (Ripple) Counters Example: 3-bit ripple binary counter. K J K J Q 0 Q 1 Q 0 FF1 FF0 C C K J Q 1 C FF2 Q 2 CLK HIGH 4 3 2 1 CLK Q 0 Q 1 1 1 1 1 0 0 0 0 0 0 8 7 6 5 1 1 0 0 1 1 0 0 Q 2 0 0 0 0 1 1 1 1 0 Recycles back to 0
CS1104-13 Asynchronous (Ripple) Counters 10 Asynchronous (Ripple) Counters Propagation delays in an asynchronous (ripple- clocked) binary counter.