sample-8 - 506 MULTIPLE PROCESSOR SYSTEMS CHAP. 8 8.1...

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506 MULTIPLE PROCESSOR SYSTEMS CHAP. 8 8.1 MULTIPROCESSORS A shared-memory multiprocessor (or just multiprocessor henceforth) is a computer system in which two or more CPUs share full access to a common RAM. A program running on any of the CPUs sees a normal (usually paged) vir- tual address space. The only unusual property this system has is that the CPU can write some value into a memory word and then read the word back and get a dif- ferent value (because another CPU has changed it). When organized correctly, this property forms the basis of interprocessor communication: one CPU writes some data into memory and another one reads the data out. For the most part, multiprocessor operating systems are just regular operating systems. They handle system calls, do memory management, provide a file sys- tem, and manage I/O devices. Nevertheless, there are some areas in which they have unique features. These include process synchronization, resource manage- ment, and scheduling. Below we will first take a brief look at multiprocessor hardware and then move on to these operating systems issues. 8.1.1 Multiprocessor Hardware Although all multiprocessors have the property that every CPU can address all of memory, some multiprocessors have the additional property that every memory word can be read as fast as every other memory word. These machines are called UMA ( Uniform Memory Access ) multiprocessors. In contrast, NUMA ( Nonun- iform Memory Access ) multiprocessors do not have this property. Why this dif- ference exists will become clear later. We will first examine UMA multiproces- sors and then move on to NUMA multiprocessors. UMA Bus-Based SMP Architectures The simplest multiprocessors are based on a single bus, as illustrated in Fig. 8-1(a). Two or more CPUs and one or more memory modules all use the same bus for communication. When a CPU wants to read a memory word, it first checks to see if the bus is busy. If the bus is idle, the CPU puts the address of the word it wants on the bus, asserts a few control signals, and waits until the memory puts the desired word on the bus. If the bus is busy when a CPU wants to read or write memory, the CPU just waits until the bus becomes idle. Herein lies the problem with this design. With two or three CPUs, contention for the bus will be manageable; with 32 or 64 it will be unbearable. The system will be totally limited by the bandwidth of the bus, and most of the CPUs will be idle most of the time. The solution to this problem is to add a cache to each CPU, as depicted in Fig. 8-1(b). The cache can be inside the CPU chip, next to the CPU chip, on the processor board, or some combination of all three. Since many reads can now be
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SEC. 8.1 MULTIPROCESSORS 507 CPU CPU M Shared memory Shared memory Bus (a) CPU CPU M Private memory (b) CPU CPU M (c) Cache Figure 8-1. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories.
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This note was uploaded on 05/20/2011 for the course COP 4600 taught by Professor Yavuz-kahveci during the Spring '07 term at University of Florida.

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sample-8 - 506 MULTIPLE PROCESSOR SYSTEMS CHAP. 8 8.1...

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