PS4 - EE762-WI2011 Project Assignment #4 Theory and Design...

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EE762-WI2011 Theory and Design of Digital Computer, II Project Assignment #4 DUE: Monday, January 31 st . In this assignment you will be writing an alternative architecture for the 8 bit ALU. DO NOT Change the Entity Description for the 8 bit ALU. The testbench is in file ~degroat/ee762_assign/pr_step4.vhdl. Note that this is the same testbench as in step 3. Also note that you do not have to recompile the ENTITY as the ENTITY for the 8-bit ALU does not change for this assignment. The alternative architecture that you are to write will use a PROCESS statement to describe the operation of the ALU on a slice-by-slice basis. You will write a process that will iteratively (use a loop) compute the Cout, and Result for each slice of the 8 bits of the ALU. The Cin will be the Cout of the previous iteration. Your architecture should have a different name than the architectures of step 3. It will contain one and only one process and no other concurrent statements . You should use a process with a sensitivity list. The sensitivity list will contain all
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This note was uploaded on 05/19/2011 for the course ECE 762 taught by Professor Degroat during the Winter '11 term at Ohio State.

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