EE312_HW6

# EE312_HW6 - schematics that you have entered Q2 For the...

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METU Dept. of Electrical and Electronics Engineering EE 312 Digital Electronics 2010/2011 Take-Home Exam Part 6 Due: 27 April 2011 RESISTOR LOADED AND DEPLETION LOADED NMOS INVERTER Q1) For the NMOS inverter with resistive load R L in the figure: V DD =5V, V t =1V, K n =0.2mA/V 2 , R L =250KΩ a) Calculate the critical voltages (VOH, VOL, VIL, VIH, VM) and sketch the voltage transfer characteristics (VTC) for this NMOS inverter circuit. b) Calculate the average static power dissipation of the NMOS inverter. c) Obtain and plot the VTC, and measure rise and fall times for a 10pF load capacitor using LT-Spice circuit simulator. Use the available components in the simulator’s library. List the important parameters that you have used. Determine the critical voltages (V OH , V OL , V IL , V IH , V M ) graphically. Give the circuit
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Unformatted text preview: schematics that you have entered. Q2) For the depletion loaded NMOS inverter in the figure: V DD =5V M 1 : V t1 =1V, K n1 ’ =25μA/V 2 , (W/L) 1 =20μm/4μm M 2 : V t2 =-2V, K n2 ’ =25μA/V 2 , (W/L) 2 =10μm/4μm a) Obtain and plot the VTC, and measure critical voltages (V OH , V OL , V IL , V IH , V M ) using LT-Spice . Use the available components in the simulator’s library. b) Measure rise and fall times for a 10pF load capacitor using LT-Spice. c) Measure the average static power dissipation of this NMOS inverter for i) 10pF capacitive load , ii) 100kΩ resistive load ( between the output and ground). Comment on the effect of resistive loading on power dissipation and VTC. Give the circuit schematics that you have entered in parts a, b, and c....
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