Unformatted text preview: schematics that you have entered. Q2) For the depletion loaded NMOS inverter in the figure: V DD =5V M 1 : V t1 =1V, K n1 ’ =25μA/V 2 , (W/L) 1 =20μm/4μm M 2 : V t2 =-2V, K n2 ’ =25μA/V 2 , (W/L) 2 =10μm/4μm a) Obtain and plot the VTC, and measure critical voltages (V OH , V OL , V IL , V IH , V M ) using LT-Spice . Use the available components in the simulator’s library. b) Measure rise and fall times for a 10pF load capacitor using LT-Spice. c) Measure the average static power dissipation of this NMOS inverter for i) 10pF capacitive load , ii) 100kΩ resistive load ( between the output and ground). Comment on the effect of resistive loading on power dissipation and VTC. Give the circuit schematics that you have entered in parts a, b, and c....
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This note was uploaded on 05/24/2011 for the course EE 312 taught by Professor Umutsezen during the Spring '11 term at Hacettepe Üniversitesi.
- Spring '11
- Electronics Engineering