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dtl_ttl-4sp - Fan-out of RTL with Active Pull-up RTL with...

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1 RTL with Active Pull-up Fan-out of RTL with Active Pull-up Determined by the output high state as Q S is cut-off for low-inputs Simplified output high state Simplified input high state Simplified output-high fan-out configuration = IH OH I I N CP OUT ) SAT ( CE CC EP OUT R V V V I I = 2 / R V V I B ) SAT ( BE OUT IN = IH (min) OUT V V = B C F ) SAT ( CE CC ) SAT ( BE IH R R V V V V β + =
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2 Diode-Transistor Logic (DTL) Basic DTL Inverter Basic DTL NAND Gate Diode Modified DTL Inverter Transistor Modified DTL Inverter
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3 VTC of Transistor Modified DTL Inverter V OH = V CC V OL = V CE,O(SAT) V IH = V BE,O(SAT) + V BE,L(FA) V IL = V BE,O(FA) + V BE,L(FA) DTL Fan-out Determined by the output low state as D I is off for high-inputs Cascaded DTL = IL OL I I N RC ) SAT ( O , C OL I I I = C ) SAT ( O , CE CC RC R V V I = Path 2 ) SAT ( O , B F ) SAT ( O , C I I σβ = RD L , E O , B I I I = D ) SAT ( O , BE RD R V I = B ) SAT ( O , BE ) ON ( L , D ) FA ( L , BE CC L , E R V V V V I σ 1 = σ For maximum fan-out B )
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