lecture_notes - ELE 312 Digital Electronics Textbooks...

Info iconThis preview shows pages 1–24. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ELE 312 Digital Electronics • DeMassa and Ciccone, Digital Integrated Circuits , John Wiley & Sons. • Taub and Schilling, Digital Integrated Electronics , McGraw-Hill Textbooks
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Contents Basic Properties of Digital Integrated Circuits Diode Digital Circuits BJT Digital Circuits – Transistor modelling – State of transistor in a circuit Resistor-Transistor Logic (RTL) Diode-Transistor Logic (DTL) Transistor-Transistor Logic (TTL) Schottky Transistor – Transistor Logic (STTL) Different TTL Gates Emitter-Coupled Logic (ECL) MOS Digital Circuits •N M O S G a
Background image of page 2
3 Most important elements: Inverter and Noninverter Idealized Inverter and Voltage Transfer Characteristics( VTCs)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Propagation Delays Rise and fall times and turn-on and turn-off times
Background image of page 4
5 Power dissipation Logic Element Equivalent Circuit and Fan-out
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 Speed-power product = (Average Power Diss) x (Propagation Delay) Power - Delay Product: PD = P DISS(avg) x t P(avg) Diode Digital Circuits
Background image of page 6
7 Diodes ) 1 (e I I T D /V V S D = Shockleys Eq V D V 0 = 0.7 V for Forward Bias
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 IV Characteristics for MN Schottky diodes for PN Junction diodes SPICE model ) 1 (e I I T D /V V S D =
Background image of page 8
9 Basic Logic Gates: AND Basic Logic Gates: OR
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
10 Clamping Diodes Level shifting diodes Level Shifting Diode AND Gate Level Shifting Diode OR Gate
Background image of page 10
1 BJT Transistors BJT Fabrication Example
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Multi-Emitter Fabrication Examples NPN BJT
Background image of page 12
3 Ebers-Moll NPN BJT Model ) 1 e ( I I T BE V / V ES BE , D = ) 1 e ( I I T BC V / V CS BC , D = BC , D R BE , D E I I I α = BC , D BE , D F C I I I = C E B I I I = CS R ES F I I = = S I Reciprocity theorem transport saturation current Reverse active (RA) Forward Reverse Saturation (SAT) Forward Forward Forward active (FA) Reverse Forward Cutoff (OFF) Reverse Reverse Mode BC junction BE junction BJT Modes of Operation
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Reduced models of the operation modes (a) Cutoff (b) Forward active (c) Saturation (d) Reverse active F F F 1 α β = R R R 1 = 1 I I B F C = σ σβ IV Characteristics
Background image of page 14
5 Modes of Operation Examples β F = 65 I C , I B = ? Base and emitter voltages = ?
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 TTL Circuit Design Output-High Pull-up Driver Output-Low Pull-down Driver Discharge path and Base-Driving circuitry
Background image of page 16
7 Power Dissipation Example Resistor-Transistor Logic (RTL)
Background image of page 17

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 INVERTER Voltage Transfer Characteritics (VTC) ) FA ( BE IL V V = B C F ) SAT ( CE CC ) SAT ( BE IH R R V V V V β + = NOR NAND
Background image of page 18
9 RTL Fan-out RTL fan-out analysis
Background image of page 19

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
10 RTL fan-out analysis Maximum fan-out? = IN OUT I I N C OUT CC OUT R V V I = B ) SAT ( BE OUT IN R V V I = IH OUT V V = B C F ) SAT ( CE CC ) SAT ( BE IH R R V V V V β + =
Background image of page 20
11 RTL NONINVERTER
Background image of page 21

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
12 AND OR
Background image of page 22
1 RTL with Active Pull-up Fan-out of RTL with Active Pull-up Determined by the output high state as Q S is cut-off for low-inputs Simplified output high state Simplified input high state
Background image of page 23

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 24
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/25/2011 for the course ELECTRONIC 312 taught by Professor Umutsezen during the Spring '11 term at Hacettepe Üniversitesi.

Page1 / 98

lecture_notes - ELE 312 Digital Electronics Textbooks...

This preview shows document pages 1 - 24. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online