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ttl_gates-4sp

# ttl_gates-4sp - CC OHS V V = E 2 CS 1 CS eq R || R || R R =...

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1 Other TTL Gates Other TTL Gates AND gates NOR gates OR gates AND-OR-INVERT (AOI) gates XOR gates Schmitt Trigger Inverters and NAND gates Tri-State buffers TTL AND gate TTL AND gate - VTC

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2 TTL NOR gate Power Dissipation Example I CC(LL) = 2 mA I CC(HL) = 4.175 mA I CC(LH) = 4.175 mA P CC(avg) = 17.75 mW I CC(HH) = 3.85 mA I RB(IL) = 1 mA I RB(IH) = 675 μ A I RC(OL) = 2.5 mA TTL NAND gate TTL OR gate TTL AND gate Example: Noise margins V NMH , V NML ? Complex Logic TTL Gate Design 1. ANDing of signals Multi-emitter input BJT sections 2. ORing of signals Multiple input sections (Q I and R B ) Multiple drive splitting BJTs (Q S ) 3. If non-inverting ORing is desired Addional logic inversion circuitry 4. Totem-pole output branch AND-OR-INVERT (AOI) gate
3 Example Design a complex logic TTL gate that V OUT = V A V B + V C + V D V E V F Example Design a complex logic TTL gate that V OUT = V A V B + V C + V D V E V F TTL XOR gate Hysteresis and Schmitt Trigger Gates

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1 Hysteresis Base-Emitter coupled Schmitt Trigger Non-inverting circuit Hysteresis CC OHS

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Unformatted text preview: CC OHS V V = E 2 CS 1 CS eq R || R || R R = α V V α V V ) FA ( 2 S , BE ) SAT ( 1 S , BE CC IDS − + = 1 R R α E 1 CS + = ) FA ( 1 S , BE eq 2 CS ) SAT ( CE CC 1 CS ) SAT ( BE CC IUS V R R V V R V V V + ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − + − = ) SAT ( CE eq 2 CS ) SAT ( CE CC 1 CS ) SAT ( BE CC OLS V R R V V R V V V + ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − + − = Example Find the V OHS , V OLS , V IUS and V IDS points where R CS1 = 4k Ω , R CS2 = 2.5k Ω , and R ES = 1k Ω . V OHS = 5V V OLS = 2V V IUS = 2.5V V IDS = 1.66V R eq = 606 Ω I CS1 = 1.05mA I CS1 = 1.92mA TTL Schmitt Trigger NAND gate 5 Example Find the V OH , V OL , V IU and V ID points where R CS1 = 4k Ω , R CS2 = 2.5k Ω , and R ES = 1k Ω . V OH = 3.6V V OL = 0.2V V IUS = 2.5V V IDS = 1.66V V IU = 1.8V V ID = 0.96V TTL Tri-state Buffers TTL Tri-state Buffers Connecting TTL Tri-state buffers to a Bus 6...
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