exp_pre3 - HACETTEPE UNIVERSITY DEPARTMENT OF ELECTRICAL...

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HACETTEPE UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING ELE-314 ELECTRONICS LABORATORY III EXPERIMENT 3 RTL AND DTL LOGIC GATES 1. PURPOSE : To design the RTL "NOR" and DTL "NAND" logic gates. 2. THEORY : The procedure while designing the RTL and DTL logic gates could be summarized as follows: Initially determine the cut-off condition of the transistor and by considering the transfer characteristics of the circuit to be realized, find a relation (inequality) between the resistors. Then consider the saturation condition of the transistor. Here there exists three possible situations which are the no load condition, the cut-off or the saturation state of the stage connected as a load. The design should be held at the Worst Case Conditions (WCC). In RTL circuits the worst case of the loading is the saturation condition of the N gates connected to the output. Considering the saturation condition of the transistor, another inequality between resistors is obtained and the appropriate values are chosen by use of these two inequalities. In DTL circuits this is the cut-off condition of the N stages connected to the output. In DTL circuits, the loading condition should be taken into account. Use the following procedure to design the RTL NOR gate in Figure 2: 1. For the transistor at saturation, consider: (a) The condition I CSAT I CMAX and find an inequality for R L .
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This note was uploaded on 05/25/2011 for the course ELECTRONIC 313 taught by Professor Umutsezen during the Spring '11 term at Hacettepe Üniversitesi.

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exp_pre3 - HACETTEPE UNIVERSITY DEPARTMENT OF ELECTRICAL...

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