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HACETTEPE UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING ELE-314 ELECTRONICS LABORATORY III EXPERIMENT 4 TTL "NAND" LOGIC GATE 1. PURPOSE : To analyze TTL "NAND" gate. 2. THEORY : Given in lecture notes. Read the related chapther of Digital Integrated Circuits by Thomas Demassa. 3. PRELIMINARY WORK : The circuit diagram of the TTL NAND gate is given in Figure 1 with the input and output voltage levels present. X R 1 4 R Z R 2 3 R Y 1K 1k Q 1 2 Q 4 Q 3 Q V CC = 5v 100 1.2k 3.9k β N = 125 β R = 0.02 V D = 0.6V I CO = 1 µ A V CESAT = 0.2V V BESAT = 0.8V V BEON = 0.5V Figure 1:TTL NAND gate NOTE: Q1 is composed of two transistors which have the same collector and base but separate emitters 3.1. Show that the given circuit is a "NAND"
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