HACETTEPE UNIVERSITYDEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERINGELE-314 ELECTRONICS LABORATORY III EXPERIMENT 4 TTL "NAND" LOGIC GATE 1. PURPOSE :To analyze TTL "NAND" gate. 2. THEORY :Given in lecture notes. Read the related chapther of Digital Integrated Circuits by Thomas Demassa.3. PRELIMINARY WORK :The circuit diagram of the TTL NAND gate is given in Figure 1 with the input and output voltage levels present. XR14RZR23RY1K1kΩQ12Q4Q3QVCC= 5v100Ω1.2kΩ3.9kΩβN= 125 βR= 0.02 VD= 0.6V ICO= 1 µA VCESAT= 0.2V VBESAT= 0.8V VBEON= 0.5V Figure 1:TTL NAND gate NOTE: Q1 is composed of two transistors which have the same collector and base but separate emitters 3.1.Show that the given circuit is a "NAND"
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