- ELE749 L05 Basic MIPS Architecture.1 Lecture 05 Basic MIPS Architecture Review Ali Ziya Alkar ELE749 Computer Organization and Design[Adapted

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Unformatted text preview: ELE749 L05 Basic MIPS Architecture.1 Lecture 05: Basic MIPS Architecture Review Ali Ziya Alkar ELE749 Computer Organization and Design [Adapted from Computer Organization and Design , Patterson & Hennessy, © 2005, UCB] ELE749 L05 Basic MIPS Architecture.2 Review: THE Performance Equation ¡ Our basic performance equation is then CPU time = Instruction_count x CPI x clock_cycle or Instruction_count x CPI clock_rate CPU time = ----------------------------------------------- ¡ These equations separate the three key factors that affect performance z Can measure the CPU execution time by running the program z The clock rate is usually given in the documentation z Can measure instruction count by using profilers/simulators without knowing all of the implementation details z CPI varies by instruction type and ISA implementation for which we must know the implementation details ELE749 L05 Basic MIPS Architecture.3 So the first area of craftsmanship is in trading function for size. … The second area of craftsmanship is space-time trade-offs. For a given function, the more space, the faster. The Mythical Man-Month , Brooks, pg. 101 ELE749 L05 Basic MIPS Architecture.4 ¡ Our implementation of the MIPS is simplified z memory-reference instructions: lw, sw z arithmetic-logical instructions: add, sub, and, or, slt z control flow instructions: beq, j ¡ Generic implementation z use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) z decode the instruction (and read registers) z execute the instruction ¡ All instructions (except j ) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 Decode Exec ELE749 L05 Basic MIPS Architecture.5 Clocking Methodologies ¡ The clocking methodology defines when signals can be read and when they are written z An edge-triggered methodology ¡ Typical execution z read contents of state elements z send values through combinational logic z write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle ¡ Assumes state elements are written on every clock cycle; if not, need explicit write control signal z write occurs only when both the write control is asserted and the clock edge occurs ELE749 L05 Basic MIPS Architecture.6 Fetching Instructions ¡ Fetching instructions involves z reading the instruction from the Instruction Memory z updating the PC to hold the address of the next instruction Read Address Instruction Instruction Memory Add PC 4 z PC is updated every cycle, so it does not need an explicit write control signal z Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal ELE749 L05 Basic MIPS Architecture.7 Decoding Instructions ¡ Decoding instructions involves z sending the fetched instruction’s opcode and function field bits to the control unit Write Data Read Addr 1 Read Addr 2...
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This note was uploaded on 05/25/2011 for the course ELECTRONIC 749 taught by Professor Aliziyaalkar during the Spring '11 term at Hacettepe Üniversitesi.

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- ELE749 L05 Basic MIPS Architecture.1 Lecture 05 Basic MIPS Architecture Review Ali Ziya Alkar ELE749 Computer Organization and Design[Adapted

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