ele74906mipspipeline - CSE 431 Computer Architecture Fall...

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ELE749 Hacettepe University 1 CSE 431 Computer Architecture Fall 2005 Lecture 06: Basic MIPS Pipelining Review Ali Ziya Alkar ELE749 Computer Organization and Design [Adapted from Computer Organization and Design , Patterson & Hennessy, © 2005, UCB]
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ELE749 Hacettepe University 2 Review: Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to stage register overhead
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ELE749 Hacettepe University 3 How Can We Make It Even Faster? ± Split the multiple instruction cycle into smaller and smaller steps z There is a point of diminishing returns where as much time is spent loading the state registers as doing the work ± Start fetching and executing the next instruction before the current one has completed z Pipelining – (all?) modern processors are pipelined for performance z Remember the performance equation: CPU time = CPI * CC * IC ± Fetch (and execute) more than one instruction at a time z Superscalar processing – stay tuned
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ELE749 Hacettepe University 4 A Pipelined MIPS Processor ± Start the next instruction before the current one has completed z improves throughput - total amount of work done in a given time z instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 IFetch Dec Exec Mem WB lw Cycle 7 Cycle 6 Cycle 8 sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB - clock cycle (pipeline stage time) is limited by the slowest stage - for some instructions, some stages are wasted cycles
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ELE749 Hacettepe University 5 Single Cycle, Multiple Cycle, vs. Pipeline Multiple Cycle Implementation: Clk Cycle 1 IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type lw IFetch Dec Exec Mem WB Pipeline Implementation: IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2
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ELE749 Hacettepe University 6 MIPS Pipeline Datapath Modifications ± What do we need to add/modify in our MIPS datapath? z State registers between each pipeline stage to isolate them Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 16 32 ALU Shift left 2 Add Data Memory Address Write Data Read Data IFetch/Dec Dec/Exec Exec/Mem Mem/WB IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack System Clock Sign Extend
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ELE749 Hacettepe University 7 Pipelining the MIPS ISA ± What makes it easy z all instructions are the same length (32 bits) - can fetch in the 1 st stage and decode in the 2 nd stage z few instruction formats (three) with symmetry across formats - can begin reading register file in 2 nd stage z
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This note was uploaded on 05/25/2011 for the course ELECTRONIC 749 taught by Professor Aliziyaalkar during the Spring '11 term at Hacettepe Üniversitesi.

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ele74906mipspipeline - CSE 431 Computer Architecture Fall...

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