L7+8 - Mani B. Srivastava UCLA - EE VHDL: A Tutorial! 2 mbs...

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Mani B. Srivastava UCLA - EE VHDL: A Tutorial! 2 mbs OUTLINE n Introduction to the language- simple examples n VHDL’s model of a system- its computation model: processes, signals and time n Language features n VHDL for logic and queue simulation 3 mbs WHAT IS VHDL? Programming Language + Hardware Modelling Language It has all of the following:- Sequential Procedural language: PASCAL and ADA like- Concurrency: statically allocated network of processes- Timing constructs- Discrete-event simulation semantics- Object-oriented goodies: libraries, packages, polymorphism 4 mbs A NAND Gate Example-- black-box definition ( interface ) entity NAND is generic ( Tpd : time := 0 ns ); port ( A, B : in bit ; Y : out bit ); end entity ;--an implementation ( contents ) architecture BEHAVIOR_1 of NAND is begin Y <= A nand B after Tpd; end BEHAVIOR_1; Important Concepts entity architecture generic port waveform assignment A B Y 5 mbs Another Implementation of NAND--there can be multiple implementations architecture BEHAVIOR_2 of NAND is signal X : bit ; begin-- concurrent statements Y <= X after Tpd; X <= ‘1’ when A=’0’ or B=’0’ else ‘0’; end BEHAVIOR_2; Important Concepts multiple architectures signal concurrent statements A B Y 6 mbs Yet More NAND Gates!!! entity NAND_N is generic ( N : integer := 4; Tpd : time); port ( A, B : in bit_vector(1 to N); Y : out bit_vector(1 to N)); end NAND_N; architecture BEHAVIOR_1 of NAND_N is begin process variable X : bit_vector(1 to N); begin X := A nand B; Y <= X after Td; wait on A, B; end process ; end BEHAVIOR_1; Important Concepts process variable wait sequential statements events 7 mbs The process Statement [label:] process [(sensitivity_list)] [declarations] begin {sequential_statement} end process [label]; • It defines an independent sequential process which repeatedly executes its body. • Following are equivalent: process (A,B) process begin begin C <= A or B; C <= A or B; end ; wait on A, B; end ; • No wait statements allowed in the body if there is a sensitivity_list. 8 mbs The wait Statement wait [ on list_of_signals ] [ until boolean_expression ] [ for time_expression ] ; This is the ONLY sequential statement during which time advances! examples:-- wait for a rising or falling edge on CLK wait on CLK; wait until CLK’EVENT; -- this is equivalent to the above-- wait for rising edge of CLK wait on CLK until CLK=’1’; wait until CLK=’1’; -- this is equivalent to the above-- wait for 10 ns wait unti l 10 ns;-- wait for ever (the process effectively dies!) wait ; 9 mbs A Simple Producer-Consumer Example entity producer_consumer is end producer_comsumer; architecture two_phase of producer_consumer is signal REQ, ACK : bit; signal DATA : integer; begin P: process begin DATA <= produce(); REQ <= not REQ; wait on ACK; end P; C: process begin wait on REQ; consume(DATA); ACK <= not ACK; end C; end two_phase; P C DATA REQ ACK 10 mbs Producer-Consumer contd. : 4-ϕ case architecture four_phase of...
View Full Document

This note was uploaded on 05/25/2011 for the course ELECTRONIC 749 taught by Professor Aliziyaalkar during the Spring '11 term at Hacettepe Üniversitesi.

Page1 / 33

L7+8 - Mani B. Srivastava UCLA - EE VHDL: A Tutorial! 2 mbs...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online