VHDL2004 - VHDL VHDL Hacettepe University Department of...

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VHDL VHDL Hacettepe University Hacettepe University Department of Electrical & Electronics Engineering Department of Electrical & Electronics Engineering Dr. Ali Ziya Alkar Dr. Ali Ziya Alkar
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Dr. Ali Ziya Alkar Intel 4000 & Pentium II Intel 4000 & Pentium II
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Dr. Ali Ziya Alkar Big picture? Big picture? Evolution in Transistor Count Evolution in Complexity
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Dr. Ali Ziya Alkar Phases of a Design Phases of a Design
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Dr. Ali Ziya Alkar Abstration Abstration Levels Levels n+ n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM d and c b a = f Out <= not(a and b and c and d); d); c, b, map(a, port nand4 : u1
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Dr. Ali Ziya Alkar Levels in Design Levels in Design Out <= not(a and b and c and d); d and c and b and a = f
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Dr. Ali Ziya Alkar V V ery ery H H igh igh S S pe pe ed ed I I ntegrated ntegrated C C ircuit ircuit H H ardware ardware D D escription escription L L anguage anguage ± VHDL can be used for VHDL can be used for documentation documentation verification verification synthesis of large digital designs synthesis of large digital designs Save time & effort for debugging
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Dr. Ali Ziya Alkar VHDL VHDL ± VHDL is a standard (VHDL-1076) developed by the IEEE. ± First revised in 1987 (Std 1076-1987) then again as VHDL'93. ± Initially created for accurate modeling of circuits for simulation ± Supports Hierarchy and uses Concurrency. ± Supports structural, dataflow and behavioral description styles ± Flexible Design Methodologies ± Not Technology Specific but supports technology specific functions. ± No need to learn a different language for design/simulation/synthesis ± Design philosophies: Top down, bottom up and mixed ± Various digital modeling techniques can be modeled easily. ± Test Benches can also be written in VHDL ± Represents not only functionality but area + speed by the user ± Capability of defining new data types
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Dr. Ali Ziya Alkar Styles of Styles of Modelling Modelling Structural Structural : Hierarchical arrangement of interconnected components. Behavioral: Behavioral: Functional Representation of Action and Timing Data Flow: Data Flow: Behavior is shown as a series of register assignments Algorithmic Algorithmic Behavior is described in terms of programmatic transformations.
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Dr. Ali Ziya Alkar Top Down Design Top Down Design Design Entry Simulation Results? Synthesis/Optimization Placement and route Results? yes yes no no Back annotate netlist/ post layout simulate Physical Design Logical Design start no
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Dr. Ali Ziya Alkar A VHDL Design A VHDL Design ± Entity Declaration ± Architecture Body ± Configuration Declaration ± Package Declaration ± Package Body
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Dr. Ali Ziya Alkar VHDL Data Types VHDL Data Types The most common VHDL data types are listed below: bit : a 1-bit value representing a wire, possible values '0' or '1' bit_vector : an array of bits real : largest range possible, floating point value integer : normal arithmetic functions can be applied, typically implemented as a 32-bit data type enumerated : user defined types physical : time, voltage, etc.
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VHDL2004 - VHDL VHDL Hacettepe University Department of...

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